About the Team

Mueon's Thermal Systems Engineering team develops advanced cooling technologies that enable the next generation of AI computing platforms. The team works across silicon, packaging, power delivery, mechanical engineering, and platform architecture to co-design hardware where cooling is an integral part of system performance. From component-level thermal management to tray- and rack-scale cooling architectures, the team develops innovative solutions that enable higher compute density, improved efficiency, and greater system reliability.

About the Role

We're looking for a Thermal Systems Engineer or Lead to develop advanced cooling solutions for Mueon's next-generation AI computing platforms. In this role, you'll partner closely with silicon architects, package engineers, power delivery engineers, mechanical designers, and manufacturing partners to develop liquid cooling systems that maximize performance, reliability, and manufacturability.

This is a hands-on technical role for someone who enjoys solving complex thermal challenges across the entire system—from silicon and cold plates to trays, coolant distribution, and rack-level integration. Depending on experience, this role may be filled at either the Senior Engineer or Technical Lead level.

Responsibilities

• Lead the design and development of advanced liquid cooling solutions for high-performance AI computing platforms
• Define thermal architectures spanning silicon, packages, boards, trays, and rack-level systems
• Own cooling solutions from concept through production, including cold plate design, supplier engagement, manufacturing, qualification, and production release
• Develop and execute thermal characterization plans to evaluate cooling performance, pressure drop, thermal resistance, reliability, and manufacturability
• Collaborate with silicon, packaging, power delivery, mechanical, and platform engineering teams to optimize overall system performance
• Drive design tradeoffs across thermal performance, reliability, manufacturability, serviceability, and cost
• Work with suppliers and manufacturing partners to develop scalable, production-ready cooling solutions
• Support hardware bring-up, thermal characterization, and root-cause analysis during system development
• Develop thermal design guidelines, specifications, and qualification methodologies for future products
• Contribute to Mueon's long-term cooling technology roadmap

You Might Thrive in This Role If You Have

• Experience designing liquid cooling solutions for high-power computing or AI systems
• A strong understanding of heat transfer, fluid dynamics, thermal interface materials, and cooling system architecture
• Experience taking thermal hardware from concept through manufacturing and production
• Enjoy collaborating across silicon, packaging, electrical, mechanical, and manufacturing organizations
• Experience balancing thermal performance, reliability, manufacturability, and cost in complex engineering systems
• Experience evaluating emerging cooling technologies including two-phase cooling, microchannel cold plates, vapor chambers, or direct liquid cooling
• A passion for developing innovative thermal solutions that enable next-generation computing platforms

Qualifications

• B.S. or M.S. in Mechanical Engineering or a related field (or equivalent experience)
• 7+ years of experience developing thermal management solutions for high-performance electronics
• Experience designing, manufacturing, and validating single-phase liquid cooling systems for production hardware
• Strong understanding of thermal characterization, experimental methods, and cooling system design
• Experience collaborating across mechanical, electrical, silicon, packaging, manufacturing, and system engineering teams

Preferred Qualifications

• Experience designing microchannel cold plates or advanced cold plate technologies
• Experience with vapor chambers, advanced heat spreaders, or next-generation thermal interface technologies
• Experience designing tray-, server-, or rack-scale cooling systems
• Experience developing qualification plans and reliability methodologies for liquid cooling hardware
• Experience with cooling system components including manifolds, pumps, hoses, quick disconnects, and coolant distribution systems
• Experience with CFD tools such as Ansys Fluent, Icepak, STAR-CCM+, or equivalent
• Experience working with thermal suppliers and contract manufacturers to transition products into high-volume manufacturing
• Experience developing two-phase cooling solutions

About Mueon

Mueon is creating an exponential computing platform to architect and deliver foundational technologies that will power the future of computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing computing products and technologies over the last three decades.

About the Team

Mueon's Silicon Engineering team develops advanced silicon and system-level solutions purpose-built for the demands of next-generation AI and data-center workloads. The team is responsible for architecting and delivering high-performance, high-power-density SoCs that tightly integrate compute, memory, power delivery, and advanced packaging technologies. We work across the full stack — from architecture and RTL through physical design and system integration — to build foundational hardware platforms that will power the future of AI.

About the Role

We're seeking a Package & Board Electrical Design Engineer to lead the electrical design of advanced semiconductor packages and system boards for Mueon's next-generation AI platforms. In this role, you'll partner closely with silicon architects, package designers, mechanical engineers, and manufacturing teams to develop high-performance package and board solutions that deliver exceptional signal integrity, power integrity, and manufacturability.

This is a hands-on technical role for someone who enjoys solving complex electrical challenges across the entire system—from die escape routing and package design to high-speed board architecture and system integration.

Responsibilities

• Design advanced package substrates for large, high-performance SoCs, chiplet-based architectures, and multi-die systems
• Develop package and board stackups that balance signal integrity, power integrity, manufacturability, thermal performance, and cost
• Define escape routing strategies for high-density interfaces including HBM, UCIe, PCIe, Ethernet, and high-speed SerDes
• Design high-speed server and accelerator boards supporting advanced AI systems
• Collaborate with silicon, package, mechanical, and manufacturing teams to optimize complete system integration
• Perform signal integrity and power integrity analysis to ensure robust operation across high-speed interfaces and power delivery networks
• Develop package and board design guidelines, routing methodologies, KOZs and design rules that improve quality and scalability
• Support bring-up, debug, and characterization of prototype hardware through production
• Work with substrate, PCB, connector, and manufacturing partners throughout design and product development

You Might Thrive in This Role If You Have

• Experience designing advanced semiconductor packages and high-speed boards for large compute systems
• A strong understanding of how silicon, packages, and boards interact to determine overall system performance
• Experience solving challenging signal integrity and power integrity problems at multi-gigabit data rates
• Enjoy collaborating across silicon, packaging, mechanical, manufacturing, and system engineering disciplines
• A passion for developing elegant electrical architectures that enable next-generation computing platforms

Qualifications

• B.S. or M.S. in Electrical Engineering or equivalent experience
• 5+ years of experience designing advanced package substrates, server boards, or high-speed computing systems
• Experience with package design and PCB layout tools such as Cadence Allegro Package Designer, Allegro X, Siemens Xpedition, or equivalent
• Strong understanding of signal integrity, power integrity, transmission line theory, and high-speed digital design
• Experience with advanced package technologies including flip-chip, 2.5D integration, silicon interposers, chiplets, or high-density organic substrates
• Experience working with high-speed interfaces such as PCIe, UCIe, Ethernet, DDR, HBM, or high-speed SerDes
• Experience collaborating with silicon design, package engineering, manufacturing, and system architecture teams through product development

Preferred Qualifications

• Experience designing accelerator, networking, or server-class hardware
• Experience with SI/PI simulation tools such as Cadence Sigrity, Ansys SIwave, HFSS, ADS, or equivalent
• Experience with advanced packaging technologies including EMIB, CoWoS, Foveros, or hybrid bonding
• Familiarity with power delivery architecture for high-current AI accelerators
• Experience supporting hardware bring-up, validation, and manufacturing

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's Silicon Engineering team develops advanced silicon and system-level solutions purpose-built for the demands of next-generation AI and data-center workloads. The team is responsible for architecting and delivering high-performance, high-power-density SoCs that tightly integrate compute, memory, power delivery, and advanced packaging technologies. We work across the full stack — from architecture and RTL through physical design and system integration — to build foundational hardware platforms that will power the future of AI.

About the Role

We are looking for a Senior Memory Architect to define and drive the memory architecture for Mueon's next-generation AI platforms.

This is not an incremental role. You will work on first-principles problems: bandwidth scaling, latency hiding, data orchestration, and memory-compute balance at system scale. You will operate across chip and system boundaries, influencing architecture from early concept through silicon and deployment.

You will be expected to lead technically, drive clarity in ambiguous spaces, and make high-impact architectural decisions that shape the trajectory of Mueon's products.

Responsibilities

• Define next-generation memory system architectures for AI/HPC SoCs, including hierarchy, caching, coherence, and data movement
• Drive architectural tradeoffs across performance, power, area, programmability, and scalability
• Identify and break fundamental bottlenecks in bandwidth, latency, and memory efficiency for large-scale AI workloads
• Develop and guide performance modeling frameworks to evaluate architectural directions
• Lead cross-functional efforts spanning RTL, physical design, firmware, and system software
• Influence hardware-software co-design, including APIs, runtime behavior, and memory management strategies
• Debug and root-cause performance gaps across simulation and silicon
• Contribute to long-term architectural roadmap and technical strategy

You Might Thrive in This Role If You Have

• Deep expertise in memory system architecture (cache hierarchies, interconnects, coherence, MMU, prefetching, or dataflow systems)
• Strong intuition for system-level tradeoffs in high-performance, power-constrained environments
• Proven ability to drive architecture from concept through implementation and bring-up
• Experience working on complex SoCs (CPU, GPU, or accelerators) at scale
• Ability to operate across abstraction layers — from microarchitecture to system behavior
• Track record of influencing or leading cross-functional engineering efforts

Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 8+ years of experience in architecture with a focus on memory systems or data movement
• Strong experience with performance modeling, simulation, and workload analysis
• Demonstrated impact on shipped silicon or large-scale systems

Preferred Qualifications

• Experience with AI/ML workloads and data center-scale systems
• Familiarity with HBM, DDR, CXL, or emerging memory technologies
• Experience with memory coherence protocols in large-scale systems
• Background in hardware/software co-design and system architecture
• Strong coding and modeling skills (C++, Python, or similar)

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's Silicon Engineering team develops advanced silicon and system-level solutions purpose-built for the demands of next-generation AI and data-center workloads. The team is responsible for architecting and delivering high-performance, high-power-density SoCs that tightly integrate compute, memory, power delivery, and advanced packaging technologies. We work across the full stack — from architecture and RTL through physical design and system integration — to build foundational hardware platforms that will power the future of AI.

About the Role

We are seeking a Post-Silicon Lead to drive bring-up, validation, and characterization of Mueon's next-generation silicon. You will play a hands-on role in early silicon bring-up while defining the methodologies, lab infrastructure, and processes required to scale post-silicon validation.

This is a leadership role with the opportunity to build and shape Mueon's post-silicon function—from initial prototypes through production readiness. You will work cross-functionally with RTL, analog, firmware, systems, and product teams to ensure successful silicon execution.

Responsibilities

• Lead bring-up and validation of early silicon prototypes
• Develop validation strategies to verify functionality, performance, power, and reliability
• Define IP- and subsystem-level characterization requirements with design teams
• Design and execute characterization plans and DOE across PVT conditions and workloads
• Perform deep silicon debug across hardware, firmware, and system layers
• Analyze validation data to drive insights and inform design improvements
• Establish post-silicon infrastructure, including lab environments, instrumentation, and automation
• Define scalable validation methodologies, workflows, and documentation standards
• Partner closely with cross-functional teams to resolve silicon issues and improve product quality
• Build and lead the post-silicon validation team as the organization scales

You Might Thrive in This Role If You Have

• Extensive experience bringing up and validating complex SoCs or large IP subsystems
• Deep expertise in silicon debug and characterization methodologies
• Comfort working across hardware, firmware, and system layers
• Strong intuition for performance, power, and reliability tradeoffs
• Experience building infrastructure, processes, and teams from the ground up
• Ability to thrive in highly cross-functional, fast-paced environments
• A strong sense of ownership driven by quality and execution

Qualifications

• B.S. or M.S. in Electrical Engineering or a related field (or equivalent experience)
• 15+ years of experience in post-silicon validation, bring-up, or characterization
• Proven track record of delivering complex silicon through validation to production
• Hands-on experience with silicon validation labs and instrumentation
• Ability to debug issues across hardware, firmware, and system software

Bonus

• Experience building validation teams or infrastructure in startup environments
• Background in high-speed interfaces, mixed-signal systems, power management, or HPC silicon
• Experience with memory IP characterization
• Strong statistical analysis and data modeling skills

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's PHY and Interconnect team designs high-speed communication interfaces that enable scalable AI systems across advanced SoCs and packaging technologies. The team works across architectural, micro-architectural, analog, digital, firmware, and system domains to deliver robust, high-bandwidth PHY enhancements and solutions for next-generation platforms.

About the Role

We're looking for a Senior Mixed-signal and PHY Design Engineer to lead the design and micro-architecture of high-speed PHY subsystems. In this role, you'll design and integrate DDR-like and/or SerDes-like PHY IP that pushes the limits of bandwidth, power efficiency, and system integration. Familiarity with all the signal integrity techniques of high-speed interfaces is a must. Protocol and Link layer functionality and requirements of one or two prevalent high-speed interconnect standards, especially UCIe3, LPDDR, HBM4 and XSR links is a desired capability.

You'll work closely with architects, analog and digital designers, power delivery, thermal, firmware engineers, and packaging teams to deliver production-ready PHY solutions and support silicon bring-up across multiple tape-outs.

Responsibilities

• Lead the design and micro-architecture of mixed-signal PHY subsystems for high-speed interconnects.
• Design high-speed analog circuits for DDR-like and/or SerDes-like PHYs, including equalization and training circuits.
• Collaborate with system, power delivery, and packaging teams to meet link-level requirements.
• Develop and support digital timing, calibration, and both standard or proprietary training architectures.
• Contribute to PHY training and bring-up Firmware flows, including validation and silicon debug, across multiple generations.
• Interpret and implement electrical and timing specifications such as DDR, UCIe and related standards.

You Might Thrive in This Role If You Have

• Deep experience designing and delivering high-speed PHY IPs to production.
• Strong mixed-signal intuition across analog, digital, and system boundaries.
• Experience with DDR, SerDes, or advanced die-to-die interconnects.
• Comfort working across circuit design, RTL, firmware, and validation teams.
• A desire to own complex subsystems from concept through silicon.

Qualifications

• M.S. or Ph.D. in Electrical Engineering or equivalent experience
• 10+ years of experience in mixed-signal circuit and PHY design

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's Analog and Mixed-Signal team develops critical analog infrastructure that enables high-performance, high-power-density AI systems. The team works across circuits, layout, packaging, and systems to ensure that sensitive analog IP integrates cleanly into large-scale SoCs operating at the limits of modern process technologies.

About the Role

We're looking for an Analog Layout Lead to own the physical realization of critical analog and mixed-signal IP across Mueon's silicon platforms. In this role, you'll partner closely with analog designers and system teams to translate circuit intent into robust, production-ready layout that meets performance, noise, and reliability goals.

This is a hands-on technical leadership role for someone who treats analog layout as a first-class design discipline and cares deeply about silicon quality.

Responsibilities

• Lead full-custom analog and mixed-signal layout for critical IP blocks across advanced CMOS and FinFET nodes
• Partner with analog designers to co-optimize circuits and layout from early design through tape-out
• Own block-level floorplanning, routing, and layout methodology for sensitive analog paths
• Drive physical verification and signoff, including DRC, LVS, EM/IR, antenna, and reliability checks
• Analyze parasitic extraction results and support post-layout performance closure
• Deliver signoff-clean GDSII and support tape-out, foundry interactions, and ECO cycles
• Mentor other layout engineers and help establish scalable layout best practices

You Might Thrive in This Role If You Have

• Deep experience laying out precision analog and mixed-signal circuits that work in silicon
• Strong intuition for device matching, noise isolation, parasitics, and layout-dependent effects
• Comfort working at the intersection of circuits, process technology, and physical design
• Experience collaborating across analog design, verification, and system teams
• A strong sense of craftsmanship and ownership over layout quality

Qualifications

• B.S. or M.S. in Electrical Engineering or equivalent experience
• 10+ years of hands-on analog or mixed-signal layout experience

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's Silicon Engineering team builds custom silicon platforms designed to meet the performance, efficiency, and scalability demands of next-generation AI and data-center systems. We work closely across architecture, physical design, packaging, and system teams to co-design hardware that scales with rapidly evolving AI workloads.

About the Role

We're looking for an RTL Design Lead to drive the front-end design of Mueon's next-generation SoCs. In this role, you'll translate architectural intent into high-quality, production-ready RTL for core compute, memory, and interconnect subsystems. You'll work closely with architects, verification engineers, and physical design teams to ensure designs are efficient, correct, and ready for silicon.

This is a hands-on role with significant ownership across microarchitecture definition, RTL implementation, and cross-functional execution.

Responsibilities

• Design and implement clean, synthesizable RTL for major SoC subsystems using Verilog/SystemVerilog
• Collaborate with architects to define and document microarchitecture for next-generation designs
• Drive design decisions that balance performance, power, and area across large-scale systems
• Partner with verification teams to ensure functional correctness through simulation and formal methods
• Work closely with synthesis and STA teams to support timing closure and implementation readiness
• Review and maintain design documentation, including microarchitecture specs and implementation notes
• Participate in design reviews and support silicon bring-up across the full development lifecycle

You Might Thrive in This Role If You Have

• Extensive experience delivering complex RTL blocks or full SoCs to tape-out
• Strong understanding of digital design fundamentals, including pipelining, FSMs, and clocking
• Experience working across architecture, verification, and physical design boundaries
• Familiarity with synthesis, STA, CDC analysis, and low-power design techniques
• A systems mindset and ability to reason from architectural goals down to RTL implementation
• A strong sense of ownership and a desire to build high-quality, scalable hardware platforms

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience
• 8+ years of experience in RTL design and digital logic development

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.

About the Team

Mueon's Physical Design team develops the implementation methodologies that enable next-generation AI computing platforms. The team works closely with architecture, RTL design, verification, DFT, and silicon engineering to transform complex digital designs into production-ready silicon. From synthesis and floorplanning through timing closure and tapeout, the team is responsible for delivering high-performance, power-efficient designs across advanced semiconductor process technologies.

About the Role

We're looking for a Back-End ASIC Engineer specializing in Static Timing Analysis to drive timing closure across Mueon's next-generation AI accelerators and supporting silicon. In this role, you'll partner closely with RTL designers, physical design engineers, DFT engineers, and verification teams to develop robust timing methodologies and ensure successful timing closure from block implementation through full-chip signoff.

This is a hands-on technical role for someone who enjoys solving challenging timing problems, developing scalable methodologies, and optimizing complex designs to achieve aggressive performance, power, and schedule goals.

Responsibilities

• Perform static timing analysis for complex digital ASICs at both block and full-chip levels across functional, test, and low-power operating modes
• Develop, review, and maintain timing constraints, including clock definitions, timing exceptions, multicycle paths, and false paths
• Drive timing closure by identifying and resolving setup, hold, clock skew, and critical path issues in collaboration with synthesis and physical design teams
• Perform signoff timing analysis including MCMM verification, OCV/AOCV/POCV analysis, and signal integrity-aware timing closure
• Collaborate with clock tree synthesis and physical implementation teams to improve timing quality of results and overall design performance
• Support engineering change order (ECO) development and implementation to achieve timing closure while minimizing design impact
• Develop automation, scripts, and methodologies that improve timing analysis efficiency, constraint quality, and signoff robustness
• Correlate timing analysis with gate-level simulation and post-silicon characterization to improve design predictability
• Present timing status, design risks, and closure progress throughout the product development lifecycle

You Might Thrive in This Role If You Have

• Experience closing timing on large, complex ASIC or SoC designs
• A strong understanding of digital timing, clocking architectures, and physical implementation
• Enjoy collaborating across RTL, physical design, DFT, verification, and silicon engineering teams
• Experience developing timing methodologies and automation that improve engineering productivity
• Strong analytical and debugging skills with a systematic approach to solving complex timing challenges
• A passion for delivering high-performance silicon on aggressive development schedules

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience
• 5+ years of experience in ASIC physical design with a strong emphasis on static timing analysis
• Extensive experience with Synopsys PrimeTime (PT/PT-SI), Cadence Tempus, or equivalent STA tools
• Strong understanding of setup and hold analysis, clock domain crossings, timing exceptions, on-chip variation, and multi-corner multi-mode analysis
• Experience developing and debugging SDC timing constraints for complex multi-clock designs
• Experience with synthesis, place-and-route, and physical implementation flows using industry-standard EDA tools
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages

Preferred Qualifications

• Experience with advanced semiconductor process technologies (7 nm and below)
• Experience supporting full-chip timing closure and tapeout for large SoCs
• Experience with low-power implementation and UPF-aware timing analysis
• Experience with formal timing verification or CDC verification methodologies
• Experience correlating timing analysis with post-silicon characterization and hardware bring-up
• Familiarity with AI accelerators, CPUs, GPUs, networking ASICs, or other high-performance computing architectures

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing and AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create technologies and products that define the future while working alongside a team that has delivered game-changing computing products and technologies over the last three decades.

About the Team

Mueon's Physical Design team develops the implementation methodologies that transform digital designs into production-ready silicon for the next generation of AI computing platforms. The team works closely with architecture, RTL design, verification, DFT, packaging, and silicon engineering to deliver high-performance, power-efficient designs across advanced semiconductor process technologies. From RTL handoff through tapeout, the team is responsible for implementing complex digital designs that meet aggressive performance, power, area, and schedule goals.

About the Role

We're looking for an RTL-to-GDS Design Engineer to implement digital IP and SoC subsystems for Mueon's next-generation AI computing platforms. In this role, you'll partner closely with RTL designers, DFT engineers, verification teams, and senior physical design engineers to develop production-ready silicon from synthesis through final GDSII release.

This is a hands-on technical role for someone who enjoys solving challenging implementation problems, optimizing designs for performance and power, and learning the complete physical design flow from RTL through tapeout.

Responsibilities

• Implement digital IP blocks and SoC subsystems from RTL through GDSII, including synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation
• Perform static timing analysis and drive timing closure across multiple operating modes and process corners
• Debug and resolve setup, hold, congestion, signal integrity, and physical implementation issues to achieve design closure
• Develop and maintain implementation scripts, automation, and methodologies that improve engineering productivity
• Collaborate with RTL designers to optimize designs for timing, power, area, and manufacturability
• Support DFT implementation, including scan integration, BIST and ATPG requirements, and physical implementation of test structures
• Perform power analysis and support implementation of low-power design techniques including clock gating, power gating, and multi-voltage architectures
• Coordinate with physical verification teams to resolve DRC, LVS, antenna, and engineering change order (ECO) issues
• Support tapeout activities, design reviews, and signoff verification through final GDSII release
• Track implementation progress, power-performance-area (PPA) metrics, and technical risks throughout the development cycle

You Might Thrive in This Role If You Have

• Experience implementing digital ASIC or SoC designs from synthesis through physical implementation
• A strong understanding of digital implementation, timing closure, and physical design fundamentals
• Enjoy collaborating across RTL, verification, DFT, and physical design teams
• Experience balancing performance, power, and area while meeting aggressive development schedules
• Strong analytical and debugging skills with a systematic approach to solving implementation challenges
• A passion for developing high-performance silicon that enables next-generation AI computing platforms

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience
• 3-6 years of experience in RTL-to-GDS implementation for ASIC or SoC designs
• Experience with synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation using industry-standard EDA tools
• Experience with static timing analysis and multi-corner, multi-mode timing closure
• Familiarity with physical verification methodologies including DRC, LVS, and signoff flows
• Understanding of low-power implementation techniques and power analysis methodologies
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages
• Familiarity with standard ASIC implementation flows, timing libraries, and physical design databases
• Strong debugging, analytical, and communication skills

Preferred Qualifications

• Experience with advanced semiconductor process technologies (16 nm and below)
• Experience implementing AI accelerators, CPUs, GPUs, networking ASICs, or other high-performance digital designs
• Experience integrating DFT features including scan, BIST, and ATPG into physical implementation flows
• Familiarity with formal equivalence checking, EM/IR analysis, and advanced signoff methodologies
• Experience with memory subsystems, embedded SRAM, or high-bandwidth memory integration
• Experience supporting production tapeouts and silicon bring-up

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing and AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create technologies and products that define the future while working alongside a team that has delivered game-changing computing products and technologies over the last three decades.

About the Team

Mueon's Digital Design team develops the compute, memory, and interconnect technologies that power the next generation of AI computing platforms. The team works closely with architecture, verification, physical design, DFT, and silicon engineering to develop high-performance, power-efficient digital IP and SoC subsystems. From microarchitecture through silicon bring-up, the team is responsible for delivering production-ready designs across advanced semiconductor process technologies.

About the Role

We're looking for an RTL Design Engineer to develop digital logic for Mueon's next-generation AI computing platforms. In this role, you'll partner closely with architects, verification engineers, physical design engineers, and DFT teams to implement high-quality RTL that meets aggressive performance, power, area, and schedule goals.

This is a hands-on technical role for someone who enjoys translating architecture into efficient hardware, solving challenging digital design problems, and delivering silicon-ready IP for advanced SoCs.

Responsibilities

• Design and develop synthesizable RTL using Verilog and SystemVerilog for complex digital IP blocks and SoC subsystems
• Translate architectural and microarchitecture specifications into efficient, high-performance, and low-power hardware implementations
• Collaborate with verification engineers to develop verification plans, review functional coverage, and resolve design issues
• Perform module- and block-level simulation, debugging, and functional validation throughout the development cycle
• Drive RTL quality through lint, clock domain crossing (CDC), and reset domain crossing (RDC) analysis and resolution
• Partner with synthesis and physical design teams to optimize designs for timing, power, area, and manufacturability
• Support design-for-test integration, including scan implementation and RTL modifications for manufacturing test
• Participate in design reviews, code reviews, and technical discussions to improve overall design quality
• Support post-silicon bring-up, debug, and root-cause analysis as products transition into hardware
• Contribute to RTL design methodologies, coding standards, automation, and reusable design infrastructure

You Might Thrive in This Role If You Have

• Experience designing complex digital logic for ASIC or FPGA products
• A strong understanding of digital design fundamentals, computer architecture, and hardware implementation
• Enjoy collaborating across architecture, verification, physical design, and silicon engineering teams
• Experience balancing performance, power, and area while developing production-quality RTL
• Strong debugging and analytical skills with a systematic approach to solving complex design challenges
• A passion for building high-quality hardware that enables next-generation AI computing systems

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 3-5 years of experience developing RTL for ASIC or FPGA designs
• Strong proficiency with Verilog and/or SystemVerilog for RTL development
• Solid understanding of digital logic design, synchronous design techniques, and computer architecture
• Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, or equivalent
• Familiarity with lint, CDC, and RDC verification methodologies
• Working knowledge of synthesis, static timing analysis, DFT, and physical implementation flows
• Experience with scripting languages such as Python, Tcl, or Perl to improve engineering productivity
• Strong analytical, debugging, and communication skills

Preferred Qualifications

• Experience with industry-standard bus protocols including AXI, AHB, APB, PCIe, CXL, or UCIe
• Experience developing low-power RTL using clock gating, power gating, multi-voltage design techniques, or UPF
• Familiarity with formal verification, equivalence checking, or assertion-based verification methodologies
• Experience designing high-speed interfaces including DDR, HBM, Ethernet, SerDes, or other high-performance interconnects
• Experience with Git, IP-XACT, or reusable IP development methodologies
• Experience developing AI accelerators, CPUs, GPUs, networking ASICs, or other high-performance computing hardware

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing and AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create technologies and products that define the future while working alongside a team that has delivered game-changing computing products and technologies over the last three decades.

About the Team

Mueon's Physical Design team develops the implementation methodologies that transform digital designs into production-ready silicon for the next generation of AI computing platforms. The team works closely with architecture, RTL design, verification, DFT, packaging, and silicon engineering to deliver high-performance, power-efficient designs across advanced semiconductor process technologies. From RTL handoff through tapeout, the team is responsible for driving implementation quality, timing closure, power optimization, and manufacturability.

About the Role

We're looking for a Senior RTL-to-GDS Design Engineer to lead the complete digital implementation flow for Mueon's next-generation AI computing platforms. In this role, you'll partner closely with architects, RTL designers, verification engineers, DFT engineers, and physical design teams to transform complex digital designs into production-ready silicon.

This is a hands-on technical leadership role for someone who enjoys solving challenging implementation problems, driving timing and power closure, and developing scalable methodologies that enable successful tapeouts. You will own the implementation strategy for complex IP blocks and SoC subsystems while mentoring other engineers and contributing to Mueon's physical design infrastructure.

Responsibilities

• Own end-to-end RTL-to-GDS implementation for complex IP blocks and SoC subsystems, including synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff
• Develop implementation strategies that optimize performance, power, area, manufacturability, and schedule across advanced semiconductor process technologies
• Drive timing closure across multiple operating modes and process corners, resolving setup, hold, signal integrity, and clocking challenges
• Collaborate with architecture and RTL teams to influence floorplanning, power planning, and implementation decisions early in the design cycle
• Lead power optimization and signoff, including dynamic power, leakage, IR drop, electromigration, and low-power implementation methodologies
• Support DFT implementation and collaborate with test engineers to optimize scan insertion, ATPG, and physical implementation tradeoffs
• Drive physical verification closure, engineering change orders (ECOs), and tapeout readiness through final signoff
• Develop automation, scripts, and methodologies that improve implementation quality, engineering productivity, and design scalability
• Mentor junior engineers and contribute to physical design best practices across the organization
• Present implementation status, technical risks, and performance tradeoffs throughout the product development lifecycle

You Might Thrive in This Role If You Have

• Experience leading RTL-to-GDS implementation for large, high-performance ASIC or SoC designs
• A strong understanding of physical implementation, timing closure, power optimization, and advanced process technologies
• Enjoy collaborating across architecture, RTL, verification, DFT, packaging, and silicon engineering teams
• Experience developing implementation methodologies and automation that improve engineering efficiency
• Strong analytical and debugging skills with a systematic approach to solving complex physical design challenges
• A passion for building scalable implementation flows that enable next-generation AI computing platforms

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience
• 7+ years of experience leading RTL-to-GDS implementation for ASIC or SoC designs through successful tapeout
• Extensive experience with synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation using industry-standard EDA tools
• Strong expertise with static timing analysis, including MCMM timing closure, signal integrity analysis, and OCV/AOCV/POCV methodologies
• Experience with physical verification, engineering change order (ECO) implementation, and tapeout signoff
• Strong understanding of power optimization, IR drop, electromigration, and low-power implementation techniques
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages
• Demonstrated ability to lead complex implementation efforts while mentoring other engineers and driving cross-functional collaboration

Preferred Qualifications

• Experience with advanced semiconductor process technologies (10 nm and below)
• Experience implementing large AI accelerators, CPUs, GPUs, networking ASICs, or high-performance SoCs
• Experience with memory subsystems, embedded SRAM, or high-bandwidth memory integration
• Experience with formal equivalence checking, reliability analysis, and advanced signoff methodologies
• Ownership of hierarchical implementation, multi-die physical planning, die-to-die interface implementation, and package-aware floorplanning
• Experience with multi-die, chiplet-based, or 2.5D/3D integrated designs
• Experience developing physical design methodologies adopted across multiple projects or engineering teams
• Experience serving as a technical lead for physical implementation or tapeout execution

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing and AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create technologies and products that define the future while working alongside a team that has delivered game-changing computing products and technologies over the last three decades.

About the Team

Mueon's Digital Design team develops the compute, memory, and interconnect technologies that power the next generation of AI computing platforms. The SoC Verification team works closely with architecture, RTL design, firmware, physical design, DFT, and post-silicon engineering to ensure that every subsystem functions correctly before first silicon. From IP integration through full-chip verification and silicon bring-up, the team develops scalable verification methodologies that enable reliable, high-performance SoCs and advanced chiplet-based systems.

About the Role

We're looking for a Senior SoC Design Verification Engineer to lead verification of Mueon's next-generation AI accelerators and supporting silicon. In this role, you'll partner closely with architects, RTL designers, firmware engineers, DFT engineers, and post-silicon teams to develop comprehensive SoC-level verification environments that ensure functional correctness across complex compute, memory, and die-to-die subsystems.

This is a hands-on technical role for someone who enjoys understanding complete system architecture, building reusable verification infrastructure, solving challenging gate-level debug problems, and driving verification from architecture through silicon bring-up.

Responsibilities

• Own verification of complex SoC subsystems from architecture review through first silicon
• Develop reusable SystemVerilog/UVM verification environments for IP-, subsystem-, and SoC-level verification
• Develop verification plans, functional coverage models, scoreboards, assertions, and self-checking testbenches that enable verification closure
• Integrate and customize industry-standard Verification IP (VIP) for interfaces including AXI, APB, UCIe, PCIe, CXL, DDR, HBM, Ethernet, JTAG, and other high-speed protocols
• Lead gate-level simulation (GLS), SDF timing simulation, UPF-aware simulation, and regression debug to ensure silicon readiness
• Develop scalable UVM Register Abstraction Layer (RAL) infrastructure for CSR verification across large SoCs
• Collaborate closely with RTL, architecture, DFT, synthesis, firmware, and physical design teams to resolve functional issues and improve design quality
• Drive verification closure through functional coverage, code coverage, assertion coverage, regression health, and verification metrics
• Develop automation, scripting, AI-assisted workflows, and debug infrastructure that improve verification productivity and engineering efficiency
• Support post-silicon bring-up, hardware/software debug, and root-cause analysis by correlating simulation behavior with silicon results

You Might Thrive in This Role If You Have

• Experience owning SoC verification environments from IP integration through tapeout
• A strong understanding of processor-based SoC architectures, memory subsystems, debug infrastructure, and chiplet-based systems
• Experience developing reusable UVM environments that scale across multiple projects and product generations
• Enjoy collaborating across architecture, RTL, firmware, physical design, DFT, and post-silicon engineering organizations
• Experience solving difficult gate-level simulation, timing, or system integration problems
• Experience improving engineering productivity through automation, scripting, and modern AI-assisted development tools
• A passion for building verification infrastructure that enables next-generation AI computing platforms

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 7+ years of experience verifying complex ASIC or SoC designs
• Expert-level experience with SystemVerilog, UVM, and reusable verification methodology
• Experience developing and maintaining large SoC verification environments, including UVM components, scoreboards, assertions, sequences, and functional coverage
• Strong experience with gate-level simulation, SDF timing simulation, waveform analysis, regression management, and silicon correlation
• Experience integrating commercial Verification IP (VIP) and verifying complex bus protocols
• Experience with UVM Register Abstraction Layer (RAL) and large-scale CSR verification
• Experience using industry standard EDA simulation and debug tools
• Strong Python, Perl, Tcl, or equivalent scripting experience for automation and regression infrastructure
• Excellent debugging, analytical, and cross-functional communication skills

Preferred Qualifications

• 10+ years of experience verifying complex ASIC or SoC designs
• Experience verifying AI accelerators, GPUs, CPUs, networking ASICs, or large compute SoCs
• Experience with ARM-based compute subsystems or heterogeneous processor architectures
• Experience verifying UCIe, PCIe, CXL, AXI, APB, DDR, HBM, Ethernet, JTAG, or other high-speed interfaces
• Experience with DFT, DFx, JTAG, scan, and debug infrastructure
• Experience with low-power verification, UPF-aware simulation, and power management verification
• Experience supporting gate-level signoff, post-silicon validation, and hardware/software co-debug
• Experience with emulation, FPGA prototyping, or hardware-assisted verification
• Experience developing reusable verification infrastructure adopted across multiple projects or engineering teams

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing and AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create technologies and products that define the future while working alongside a team that has delivered game-changing computing products and technologies over the last three decades.

About the Team

Mueon's Silicon Engineering team develops advanced silicon and system-level solutions purpose-built for the demands of next-generation AI and data-center workloads. The team is responsible for architecting and delivering high-performance, high-power-density SoCs that tightly integrate compute, memory, power delivery, and advanced packaging technologies. We work across the full stack — from architecture and RTL through physical design and system integration — to build foundational hardware platforms that will power the future of AI.

About the Role

We're looking for a Structural Design & Full-Chip Integration Lead to drive the physical realization and backend integration of Mueon's next-generation SoCs. In this role, you'll own full-chip implementation from floorplanning through tape-out, working closely with RTL, verification, packaging, and system teams to ensure designs meet performance, power, area, and reliability goals.

This is a hands-on technical leadership role with significant ownership across design methodology, integration strategy, and execution. You'll play a central role in translating architectural intent into production-ready silicon.

Responsibilities

• Lead full-chip physical design and backend integration, including floorplanning, placement, routing, clocking, and power delivery
• Drive timing closure, power optimization, and congestion management for complex, large-scale SoCs
• Partner closely with Analog, RTL, verification, and architecture teams to ensure clean integration of complex IP blocks
• Own signoff flows including STA, DRC, LVS, IR-drop, EM, and reliability analysis
• Deliver signoff-clean GDSII for fabrication and support tape-out, foundry reviews, and post-layout ECOs
• Define, implement, and improve front-end and back-end design methodologies to enable scalable and repeatable execution
• Collaborate with packaging and system teams where physical design decisions impact power delivery, thermals, and performance
• Participate in design reviews, documentation, and silicon bring-up across the full product lifecycle

You Might Thrive in This Role If You Have

• Extensive experience delivering complex SoCs through tape-out with strong backend ownership
• Deep understanding of full-chip physical design, including synthesis, place-and-route, CTS, and timing closure
• Experience integrating large IP blocks and managing system-level physical tradeoffs
• Strong intuition for performance, power, and reliability at advanced technology nodes
• Ability to work across abstraction layers — from architecture and RTL intent to physical implementation
• Comfort collaborating across disciplines in a fast-paced, highly technical environment
• A mindset oriented toward ownership, quality, and long-term scalability of silicon platforms

Qualifications

• B.S. or M.S. in Electrical Engineering or a related field (or equivalent experience)
• 7+ years of experience in backend physical design and full-chip integration
• Proven track record of delivering production silicon in advanced process nodes

About Mueon

Mueon is creating an Exponential Computing Platform to architect and deliver foundational technologies that will power the future of Computing/AI. We value engineers who can push the limits of what silicon can do and are passionate about building high-quality products. You will have the opportunity to create the technologies and products that will define the future and also have the opportunity to work with a team that has created game changing Computing products and Technologies over the last three decades.